If I take the line in the for loop out of it and give i an integer value, the code can extract as well. I was able to determine that the issue has to do with the for loop since the code can be extracted without it. V(CLK_OUT,GND) <+ vdd_supply/2 + vdd_supply/2 * sin(phi+delta_phi) įreq_inst = freq_center + freq_range * din_digit calcualte the deviation in fet due to vin is not at the centerĭelta_phi = 2 * `MATH_PI * freq_range * idt( din_digit, 0 ) Phi = 2 * `MATH_PI * ( cycle_count - floor(cycle_count) ) ![]() calculate the phi as if running at center frequency ![]() Parameter real din_center = 127.5 // LSBĭin_digit = din_digit + ceil( V(DIN, GND) - vdd_supply/2 ) * pow(2,i) ĭin_digit = ( din_digit - din_center ) / pow(2,8) Module DCO_VA_MODEL ( DIN, GND, CLK_OUT ) When I extract it, the extraction would fail (TE-4309). I was trying to implement a digital controlled oscillator model in Verilog-A.
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